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Hrant Muradyan (grand): профессиональное резюме

Muradyan Hrant George
26. 08. 1975


Домашний телефон: 374-1-427273
Мобильный телефон: 374-1-09-49457
Email: grand@freenet.am




базовая информация об образовании

1998 –2000 State Engineering University Yerevan, Armenia
Research Post-Graduate School, Department of Solid Bodies Engineer Physics and Microelectronics.
1996 – 1998 State Engineering University Yerevan, Armenia
MS, Graduate School, Department of Electronics
MS Thesis: "Elaboration of algorithm and program of identification of EKG picks"
1992 – 1996 State Engineering University Yerevan, Armenia
4 BA, Department of Semiconductor and Biomedical Devices,
Faculty of Technical Cybernetics



дополнительные навыки (skills)

HD Design:
Altera Max Plus II 10.2, Silos III, ModelSim SE/EE 5.5, Leonardo Spectrum, Simplify Pro 7.0
Programming:
Verilog, basic knowledge of VHDL, C++, Borland Delphi 5.0, HTML, Java Script, Matlab 6.1, Basic knowledge’s in Visual C++
Mixed-signal IC Design:
Tanner EDA: T-Spice Pro 7.0, L-Edit Pro 8.2, S-Edit 7.0
General:
Adobe Photoshop, CorelDraw, CorelPhotopaint, Macromedia Flash, Allaire HomeSite, PageMaker
Operating Systems:
MS-DOS, MS-WinNT/9x/00/XP



предыдущие и настоящие места работы

2001 –present “Action” study center (www.action.am) Yerevan, Armenia
Lecturer on Verilog HDL
Working in a 6-person class as a lecturer on Verilog HDL. Course consists of 24 lessons. Preparing students for passing tests in Armenian hardware companies.
2000 – present Epygi Labs Am LLC Yerevan, Armenia
Department of IC Design
Engineer. Working in a 8-person team in complex projects, responsible for design, prototype, test bench and debug IC by Verilog HDL (used Altera Max Plus II, Silos III). For the last year work in area of analysis, simulation and layout of ICs. The tools used are Matlab and Tanner EDA.
Teaching. Classes on Verilog HDL for the company employees.
Projects: Development of specific DSP functions: CRC, Scrambler, Error Correction Code (Reed-Solomon encoder/decoder) in FPGA. Sigma-Delta ADC: research, Verilog model of decimation filter), simulation with Spice and layout. Test board design for internal use. Writing Verilog code for FPGA, this should be used for configuration Intersil base band processor. By now involved in PLL design (digital and analogue parts).
1998 – 1999 State Engineering University Yerevan, Armenia
Laboratory assistant
Senior assistant, responsible for supervision of students’ research activities. Providing lectures on "Biomedical devices" for BA students
1997 – 1998 "TROUZIK” weekly Yerevan, Armenia
Desktop publishing specialist, responsible for newspaper's layout design (used PageMaker 6.0. Quark Express 4.01)
Development of visual materials and preparation for publishing (used Photoshop)
1994 – 1995 "Diana" Cable TV Yerevan, Armenia
Line engineer
Line engineer, responsible for debug and analysis for cable network internal and external failures, general technical support
Regulation of payments




. общие данные
последняя редакция: 12.07.2007 00:00:00

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